1. Field of the Invention
The present invention relates to a method of manufacturing a layer sequence and to a method of manufacturing an integrated circuit.
2. Description of the Related Art
One of the big issues in gate patterning of logic devices for 90 nm technology lithography is the CD-difference in n-MOS and p-MOS transistors. CD, critical dimension, denotes the size of the smallest geometrical features (e.g. width of a gate stack) which can be manufactured during semiconductor manufacturing using a given technology.
When forming a gate stack for an n-MOS transistor on the one hand and for a p-MOS transistor on the other hand, the width of the gate stack usually differs between the two devices of a CMOS architecture due to an effect described in the following. Comparing undoped silicon and n-doped silicon, the chemical etching of silicon in halogen-based discharges is affected by the type and concentration of electrically active dopants. P-type doping (e.g. boron) suppresses silicon etch rate slightly (by as much as a factor of two), while high concentrations of n-typed dopants (e.g. arsenic or phosphorus) enhance etching by a factor of 1.5 to 2.
N-type doping raises the Fermi level and thereby reduces the energy barrier for charge transfer to chemisorbed chlorine.
Chlorine and/or bromine atoms, which may be used for etching a gate stack of an n-MOS or a p-MOS transistor, are covalently bound to specific sites of an undoped silicon surface. The formation of a more ionic silicon-halogen surface bond, due to the n-type sites and enhanced electron transfer, opens additional chemisorption sites and facilitates etchant penetration into the substrate lattice, which makes it possible for impinging chlorine atoms to more readily chemisorp, penetrate the lattice, and react.
When forming a CMOS device, n-MOS areas comprise a pre-implantation before being etched (e.g. phosphorus implantation), but in p-MOS areas, such a pre-implantation is not present. Consequently, when etching a gate stack for an n-MOS area and a p-MOS area, there is a difference in etch rate between n-MOS area and p-MOS area. An n-MOS area shows a higher etch rate than a p-MOS area, and finally smaller CD.
This results in different gate widths in n-MOS and p-MOS transistors yielding different electrical properties and transistor parameter values (e.g. threshold voltage) of p-MOS and n-MOS transistors in a CMOS device. Such differences are undesired, since they may deteriorate the performance of the transistor components of an integrated circuit.
In the following, the described shortcoming will be explained in more detail on the basis of FIG. 1A to FIG. 1E showing layer sequences according to a method of manufacturing a layer sequence for a CMOS device according to the prior art.
Referring to FIG. 1A to FIG. 1E, on the left hand of each of the figures, there are shown p-MOS layer sequences 100, and n-MOS layer sequences 101 are shown on the right hand side, respectively. Layer sequences 100, 101 are formed on different surface regions of the same substrate.
Layer sequence 102 shown in FIG. 1A is obtained by depositing a gate oxide layer 104 on a silicon substrate 103. Subsequently, an undoped polysilicon layer 105 is deposited on the gate oxide layer 104. Further, a photoresist layer 106 is applied to the surface of the n-MOS layer sequence 100 and of the n-MOS layer sequence 101. Subsequently, a lithography process is carried out to maintain material of the photoresist 106 only on top of the p-MOS layer sequence 100, whereas the surface of the undoped polysilicon layer 105 is free of photoresist 106 and thus exposed in the n-MOS layer sequence 101. After that, an n-type implantation 107 process is carried out implanting phosphorus material only in the undoped polysilicon layer 105 in the n-MOS layer sequence 101, whereas the photoresist 106 covering the undoped polysilicon layer 105 on the p-MOS layer sequence 100 prevents n-type dopant from being introduced in undoped polysilicon layer 105 of p-MOS layer sequence 100.
Layer sequence 110 as shown in FIG. 1B is obtained by removing photoresist 106 from the surface of layer sequence 102.
As a result of the implantation process just described, an n-doped polysilicon layer 111 is generated due to the exposure of undoped polysilicon layer 105 of the n-MOS layer sequence 101 during the implantation process. In contrast to this, the undoped polysilicon layer 105 is maintained in the CMOS layer sequence 100. FIG. 1B shows the doped polysilicon layer 111 in the n-MOS area 101 after the described gate implantation.
After having doped polysilicon layer 111 by implantation and after having removed photoresist 106, a hard mask 112 is formed by depositing silicon oxide material which is later used as an etch barrier. The thickness of the hard mask 112 is typically 500Å to 2000Å, and generally TEOS (“tetra ethyl ortho silicate”) is used as the silicon oxide material.
To obtain the layer sequence 120 shown in FIG. 1C, both areas 100, 101 are covered with a BARC-layer which is subsequently covered by a further photoresist layer. BARC means “bottom antireflective coating”. A BARC structure is used in photolithography to enhance the control of critical dimension (CD) by suppressing reflective notching, standing wave effects and the swing ratio caused by thin film interference. BARC-layer and further photoresist layer are then patterned using a lithography and an etching process to form laterally confined structures on both areas 100, 101 consisting of BARC structure 121 and photoresist structure 122.
To obtain the layer structure 130 shown in FIG. 1D, the hard mask 112 is etched on the p-MOS layer sequence 100 and on the n-MOS layer sequence 101 using the laterally confined stack of BARC structure 121 and the photoresist structure 122 as an etching mask. This results in hard mask structures 131 which are laterally confined structures on the surface of undoped polysilicon layer 105 on the one hand and on the surface of n-doped polysilicon layer 111 on the other hand. The BARC structure 121 and the photoresist structure 122 are then removed. The lateral width of the hard mask structures 131, d, is almost equal at the p-MOS layer sequence 100 and at the n-MOS layer sequence 101, since the etching rate when etching structures 112 does not differ between the p-MOS layer sequence 100 and the n-MOS layer sequence 101, due to the identical material of hard mask 112 on both areas 100, 101. In other words, after etching the hard mask 112, CD of p-MOS and n-MOS are almost the same, i.e. the length d is approximately equal in region 100 and in region 101.
To obtain the CMOS gate stack layer sequence 140 shown in FIG. 1E, a polysilicon-selective etching process is carried out. Due to the above-described effect that the etching rate is larger for the n-doped polysilicon layer 111 due to the introduced phosphorus dopant than the etching rate of the undoped polysilicon layer 105, the width d2 of the n-doped gate 142 at the n-MOS layer sequence 101 is substantially smaller than the width d1 of the undoped gate 141 of the p-MOS layer sequence 100. This is a result of the higher etch rate of the n-doped polysilicon 111 in the n-MOS area 101 as compared to the undoped (or only intrinsic doped) polysilicon 105 in the p-MOS area 100.
Thus, the p-MOS transistor shown on the left hand of FIG. 1E performs different electrical properties (threshold voltage, etc.) than the n-MOS transistor on the right hand side of FIG. 1E.
The problem of different gate stack length as described above particularly appears in 90 nm logic technology using a high energy pre-implantation scheme. Until the 130 nm technology, this problem has not been that severe.
According to the state of the art, the different widths of p-MOS and n-MOS transistors are tried to be made approximately equal by adjusting lithography CD by OPC (“optical proximity correction”). OPC is a correcting process for compensating mask errors. In other words, OPC is a means of addressing lithography distortions in semiconductor manufacturing. The goal of OPC is to produce smaller features in using a given equipment set by enhancing the printability of a waver pattern. OPC applies systematic changes to photomask geometries to compensate for non-linear distortions caused by optical diffraction and resist process effects. A mask incorporating OPC is thus a system that negates undesirable distortion effects using pattern transfer.
However, the OPC method is very expensive and difficult and substantially increases the processing time for manufacturing an integrated circuit.